This invention relates to special purpose high speed processors, commonly called hardware accelerators, which are used for computer simulations generally, and computer simulation of circuit designs in particular.
Hardware accelerators are special purpose processing apparatus that are designed specifically for an efficient realization of a particular algorithm or a class of algorithms. These elements are becoming increasingly popular as viable solutions to a wide range of computer-aided design problems, and their use has resulted in notable performance improvements. With present day simulation elements it is possible to perform over 10.sup.6 gate evaluations per second. This is orders of magnitude improvement over software logic simulations.
Simulation elements achieve their high level of performance through one or more of the following means: duplication of identical hardware units among which the simulation problem is divided, pipelining of the operations through the units, dedicated logic tailored to the application at hand, and dedicated interconnections between the processing units. A useful survey of hardware accelerators is presented in "A Survey of Hardware Accelerators used in Computer-Aided Design," Tom Blank, IEEE Design and Test of Computers, August 1984. Also instructive are "A Logic Simulation Machine", Miron Abramovici, IEEE, Vol-CAD-2, No. 2, April 1983; "Hardware Acceleration of Logic Simulation using a Data Flow Architecture", IEEE 1985; "Silicon Solutions Carves Niche in VLSI Design", Electronics, Aug. 12, 1985; "Powerspice Simulates Circuits Faster and More Accurately", Electronics, Aug. 26, 1985; and "A Hardware Architecture for Switch-Level Simulation" W. J. Dally et al., IEEE 1985.
Most of the hardware accelerators described in these prior art systems contain many processing elements, or elements, that are tailored to perform specific tasks very efficiently, and these elements are interconnected to form a cohesive, interacting system. The failings shared by all of the known simulation elements are that they employ fixed interconnections between the processing elements, which reduces their flexibility, and that the processing elements themselves are tailored to the particular application to such an extent that it is necessary to use different designs when a different application is contemplated.